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Product Data Sheet
M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL1 GND APC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC FIN_SEL0 FEC_SEL0 FEC_SEL1 FEC_SEL2 FEC_SEL3 VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19
GENERAL DESCRIPTION
The M2006-12A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. Clock multiplication ratios (including forward and inverse FEC) are pin-selected from pre-programming look-up tables. Includes Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.813) MTIE and TDEV compliance during reference clock reselection. Hitless Switching (HS) engages when a 4ns or greater clock phase change is detected.
This phase-change triggered implementation of HS is not recommended when using an unstable reference (more than 1ns jitter pk-to-pk) or when the resulting phase detector frequency is less than 5MHz.
28 29 30 31 32 33 34 35 36
M2006-12A
(Top View)
18 17 16 15 14 13 12 11 10
P0_SEL P1_SEL nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND
FEATURES
Reduced intrinsic output jitter and improved power supply noise rejection compared to M2006-12 Similar to the M2006-02A - and pin-compatible - but adds Hitless Switching and Phase Build-out functions Includes APC pin for Phase Build-out function (for absorption of the input phase change) Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation Input reference and VCSO frequencies up to 700MHz (Specify VCSO frequency at time of order) Low phase jitter of 0.25 ps rms typical (12kHz to 20MHz or 50kHz to 80MHz) Commercial and Industrial temperature grades Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package PLL Ratio 1/1 237/255 (inverse FEC)
Figure 1: Pin Assignment
Example I/O Clock Combinations
Using M2006-12A-622.0800 Input Clock (MHz) 622.08, 155.52, 77.76, or 19.44 669.3266, 167.3316, 83.6658, or 20.9165 Output Clock (MHz) 622.08 or 155.52
Table 1: Example I/O Clock Combinations Using M2006-12A-622.0800
Using M2006-12A-669.3266 PLL Ratio 237/255 (FEC rate) 1/1 Input Clock (MHz) 622.08, 155.52, 77.76, or 19.44 669.3266, 167.3316, 83.6658, or 20.9165 Output Clock (MHz) 669.3266 or 167.3316
Table 2: Example I/O Clock Combinations Using M2006-12A-669.3266
SIMPLIFIED BLOCK DIAGRAM
Loop Filter
M2006-12A
APC DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL 4 2 Mfec / Rfec Divider LUT Mfin Divider LUT P0_SEL P1_SEL 0 Rfec Div 1 Mfec Div Mfin Div
(1, 4, 8, or 32)
GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN
1 2 3 4 5 6 7 8 9
VCSO
P0 Div
(1 or 4)
FOUT0 nFOUT0
FEC_SEL3:0 FIN_SEL1:0
P1 Div
(1 or 4)
FOUT1 nFOUT1
Figure 2: Simplified Block Diagram
M2006-12A Datasheet Rev 1.0
M2006-12A VCSO Based FEC Clock PLL with Hitless Switching
Revised 28Jul2004
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M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
DETAILED BLOCK DIAGRAM
RLOOP CLOOP RPOST CPOST CPOST RLOOP CLOOP OP_OUT RPOST nOP_OUT nVC VC
External Loop Filter Components
M2006-12 A
APC DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL
MUX Phase Detector
OP_IN
nOP_IN
RIN
0
Rfec Divider
RIN Loop Filter Amplifier
1
Phase Locked Loop (PLL)
SAW Delay Line
Phase Shifter
VCSO
Mfec Divider
Mfin Divider P0 Divider FOUT0 nFOUT0
FEC_SEL3:0
4
Mfec / Rfec Divider LUT Mfin Divider LUT
P = 1 ( P0_SEL = 0 ) or 4 ( P0_SEL = 1 )
FIN_SEL1:0
2
P1 Divider
P = 1 ( P1_SEL = 0 ) or 4 ( P1_SEL = 1 )
FOUT1 nFOUT1
P0_SEL
P1_SEL
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 11, 19, 33 12, 13 15, 16 17 18 20 21 22 23 24 25 27 28 29 30 31 32 34, 35, 36 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC VCC FOUT1, nFOUT1 FOUT0, nFOUT0 P1_SEL P0_SEL nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0 APC FIN_SEL1 FIN_SEL0 FEC_SEL0 FEC_SEL1 FEC_SEL2 FEC_SEL3 DNC I/O Configuration Description
Ground Input Output Input Power Output Input Input Input Input No internal terminator Internal pull-down resistor1 Internal pull-UP resistor1 Internal pull-down resistor1 Internal pull-down resistor1 Internal pull-UP resistor1 Internal pull-down resistor Internal pull-down resistor
1 1
Power supply ground connections.
External loop filter connections. See Figure 4.
Power supply connection, connect to +3.3V. Clock output pairs. Differential LVPECL. P Divider controls. LVCMOS/LVTTL. (For P0_SEL, P1_SEL, see Table 6 on pg. 3. Reference clock input pair 1. Differential LVPECL or LVDS. Reference clock input selection. LVCMOS/LVTTL: Logic 1 selects DIF_REF1, nDIF_REF1. Logic 0 selects DIF_REF0, nDIF_REF0. Reference clock input pair 0. Differential LVPECL or LVDS. Automatic Phase Compensation (phase build-out). LVCMOS/LVTTL: Logic 1 - Device absorbs input phase transients. Logic 0 - Device doesn't absorb transients. Input clock frequency selection. LVCMOS/LVTTL. (For FIN_SEL1:0, see Table 4 on pg. 3. FEC PLL divider ratio selection. LVCMOS/ LVTTL. (For FEC_SEL3:0, see Table 5 on pg. 3.) Internal nodes. Connection to these pins can cause erratic device operation.
Table 3: Pin Descriptions
Input Input
Internal pull-down resistor1 Internal pull-UP resistor1 Do Not Connect.
Input
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M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
Post-PLL Dividers The M2006-12A also features two post-PLL dividers, one for each output pair. The "P1" divider is for FOUT1 and nFOUT1; the "P0" divider is for FOUT0 and nFOUT0. Each divides the VCSO frequency to produce one of two output frequencies (1/4 or 1/1 of the VCSO frequency). The P1_SEL and P0_SEL pins each select the value for their corresponding divider.
M2006-12A-622.0800
PLL DIVIDER LOOK-UP TABLES
Mfin Divider Look-Up Table (LUT) The FIN_SEL1:0 pins select the feedback divider value "Mfin" (for Frequency Input).
FIN_SEL1:0
Mfin Value 1* 4 8 32
M2006-12A-622.0800
1 1 0 0
1 0 1 0
Sample Ref. Freq. (MHz) 622.08 155.52 77.76 19.44
P1_SEL, P0_SEL
P Value 4 1
Table 4: Mfin Divider Look-Up Table (LUT)
Note *: Do not use with FEC_SEL3:0=1100 or 1101 or an excessive phase detector frequency will result. Note : Example with M2006-12A-622.0800 and "Non-FEC ratio" selection made from Table 5 (FEC_SEL2=1).
1 0
Sample Output Frequency (MHz) 155.52 622.08
Table 6: P Divider Selector, Values, and Frequencies
FEC PLL Ratio Dividers Look-up Table (LUT) The FEC_SEL3:0 pins select the FEC feedback and reference divider values Mfec and Rfec.
FEC_SEL3:0 Mfec Rfec1
FUNCTIONAL DESCRIPTION
The M2006-12A is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to one of two selectable input reference clocks. An internal high "Q" SAW filter provides low jitter signal performance and controls the output frequency of the VCSO (Voltage Controlled SAW Oscillator). Configurable FEC feedback and reference dividers (the "Mfec Divider" and "Rfec Divider") provide the multiplication ratios necessary to accomodate clock translation for both forward and inverse Forward Error Correction. In addition, a configurable feedback divider (labeled "Mfin Divider") provides the broader division options needed to accomodate various reference clock frequencies. For example, the M2006-12A-622.0800 (see "Ordering Information" on pg. 10) has a 622.08MHz VCSO frequency:
Description Inverse FEC ratio Inverse FEC ratio, equivalent to 237/255 Inverse FEC ratio, equivalent to 238/255 Inverse FEC ratio Non-FEC ratio, complements 0001 or 1001 2 Non-FEC ratio, complements 0010 or 1010 2 Non-FEC ratio, complements 0011 or 1011 2 FEC ratio (OTU3) FEC ratio, equivalent to 255/237 (OTU2) FEC ratio, equivalent to 255/238 (OTU1) FEC ratio Non-FEC ratio 3 Do not use these two settings with FIN_SEL1:0=11 Non-FEC ratio 3
0 0 0 0
0 0 0 0
0 0 1 1
0 1 0 1
236 79 14 239 236 79 14 239 255 85 15 255 1 2 4 8
255 85 15 255 79 14 239 236 79 14 239 1 2 4 8
0100 0101 0110 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1
236 Non-FEC ratio, complements 0000 or 1000 2
* The inverse FEC PLL ratios (at top of Table 5) enable
the M2006-12A-622.0800 to accept "base" input reference frequencies of: 663.7255, 666.5143, 669.3266, 672.1627, and 622.08MHz. The Mfin feedback divider enables the actual input reference clock to be the "base" input frequency divided by 1, 4, 8, or 32. Therefore, for the base input frequency of 622.08MHz, the actual input reference clock frequencies can be: 622.08, 155.52, 77.76, and 19.44MHz. (See Table 4 on pg. 3.)
Table 5: FEC PLL Ratio Dividers Look-up Table (LUT)
Note 1: The phase detector frequency (Fpd, which is calculated as Fref/Rfec) should be above 1.5 MHz to prevent spurs on the output clock. To ensure the PLL remains locked when using a recovered clock (such as in loop timing mode), the phase detector frequency should ideally be about 20MHz, or at least less than 50 MHz. Note 2: These table selections use the same or similar Mfec divider values as the complementary selections noted. This allows the use of the same loop filter component values and yields the same PLL loop bandwidth and damping factor values for complementary selections. Complementary selections can be actively switched in a given application. Note 3: In non-FEC applications, these settings can be used to optimize phase detector frequency or to actively change PLL loop bandwidth.
*
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The PLL The PLL uses a phase detector and configurable dividers to synchronize the output of the VCSO with selected reference clock. The "Mfin Divider" and "Mfec Divider" divide the VCSO frequency, feeding the result into the phase detector. The selected input reference clock is divided by the "Rfec Divider". The result is fed into the other input of the phase detector. The phase detector compares its two inputs. It then outputs pulses to the loop filter as needed to increase or decrease the VCSO frequency and thereby match and lock the divider output's frequency and phase to those of the input reference clock. Due to the narrow tuning range of the VCSO (+200ppm), appropriate selection of all of the following are required for the PLL be able to lock: VCSO center frequency, input frequency, and divider selections.
See also "Maintaining PLL Lock:" on pg. 4.
M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
An out-of-lock condition due to an inappropriate configuration will typically result in the VCSO operating at its lower or upper frequency rail, which is approximately 200ppm above or below the nominal VCSO center frequency.
See also "Hitless Switching (HS)" (next) for an additional issue with regard to phase locking. Hitless Switching (HS) The M2006-12A includes a proprietary Hitless Switching (HS) feature that prevents an excessive phase transient of the output clocks upon input reference rearrangement. Upon the occurance of an input reference phase change, or phase transient, PLL bandwidth is lowered by the HS function. This limits the rate of phase change in the output clocks. With proper configuration of the external loop filter, the output clocks will comply with MTIE (maximum time interval error) specifications for GR-253 (SONET) and ITU G.813 (SDH) during input reference clock change, depending on the magnitude of the resulting phase change. The HS function uses a phase error detector at the phase detector to detect a clock phase change. During normal operation with a stable reference clock, the PLL will be frequency locked and phase locked, resulting in very little error at the phase detector (<1 ns). Upon the selection of a new input reference clock at a different clock phase, a phase error will occur at the phase detector. The HS function is triggered with a phase error greater than 4 ns, upon which a narrow PLL bandwidth is applied. When the PLL locks to within 2 ns error at the phase detector, wide bandwidth (normal) operation is resumed. The HS function is not suitable for situations in which an unstable reference is used. Under normal conditions the reference clock jitter should not induce phase jitter at the phase detector beyond 2 ns. (This includes when subjecting the system to jitter tolerance compliance testing.) Because of this, the M2006-12A is not recommended for use with some Stratum DPLL clock sources, or with unstable recovered network clocks intended for loop timing configuration. It is also not recommended for complex FEC ratios where the phase detector is operated at less 1 MHz. For these applications the M2006-02A is suggested. The M2006-02A is identical to the M2006-12A except that it does not include the HS function (nor the APC pin and phase build-out function, which are discussed in the following section).
Relationship Among Frequencies and Dividers The VCSO center frequency must be specified at time of order. The relationship between the VCSO (Fvcso) frequency, the Mfin divider, the Mfec divider, the Rfec divider, and the input reference frequency (Fin) is: Mfec Fvcso = Fin x Mfin x ------------Rfec As an example, for the M2006-12A-622.0800, the non-FEC and inverse-FEC PLL ratios in Table 5 enable use with these corresponding input reference frequencies:
VCSO Clock Frequency (MHz) 622.08
M2006-12A-622.0800
/
FEC Ratio 1 /1 238 / 255 237 / 255 236 / 255
Base Input Ref. = Frequency (MHz) 1 622.0800 666.5143 669.3266 672.1627
M2006-12A-622.0800
Table 7: Example FEC PLL Rations and Input Reference Frequencies
Note 1: Input reference clock ("Fin") can be the base frequency shown divided by "Mfin" (as shown in Table 4 on pg. 3).
Maintaining PLL Lock:
The narrow tuning range of the VCSO requires that the input reference frequency must remain suitable for the current look-up table selection. For example, when switching between "Inverse FEC ratio" and "Non-FEC ratio" look-up table selections (see Table 5 on pg. 3), the input reference frequency must change accordingly in order for the PLL to lock.
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Automatic Phase Compensation (APC) Pin The M2006-12A also includes a phase build-out function that can be selectively enabled by asserting the APC input (pin 25) to logic 1. The phase build-out function works in conjunction with the HS function. When the APC pin is asserted, the phase build-out function enables the PLL to absorb most of the phase change of the input clock which reduces re-lock time and the generation of wander. (Wander is created in this case by the generation of extra output clock cycles.) When the APC pin is asserted, the phase build-out function is triggered by same >4 ns phase transient (at the phase detector) that triggers the HS function. Once triggered, a new VCSO clock edge is selected for the phase comparator feedback input. (The clock edge selected is the one closest in phase to the new input clock phase.) The residual phase detector phase error following reselection is approximately 3-to-4 ns. The narrow bandwidth selected by HS minimizes VCSO drifting and switch transients during the process. It is recommended that the APC pin remain low when the phase detector frequency is less than 4 MHz. Otherwise, the M2006-12A may have difficulty locking to reference upon power-up. Outputs The M2006-12A provides a total of two differential LVPECL output pairs: FOUT1 and FOUT0. Because each output pair has its own P divider, the FOUT1 pair and the FOUT0 can output the two different frequencies at the same time. For example, FOUT1 can output 155.52MHz while FOUT0 outputs 622.08MHz.
Any unused output should be left unconnected (floating) in the system application. This will minimize output switching current and therefore minimize noise modulation of the VCSO.
M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
External Loop Filter To provide stable PLL operation, and thereby a low jitter output clock, the M2006-12A requires the use of an external loop filter. This is provided via the provided filter pins (see Figure 4). Due to the differential signal path design, the implementation requires two identical complementary RC filters as shown here.
RLOOP CLOOP RPOST CPOST CPOST RLOOP OP_IN
4 9
CLOOP OP_OUT
8 5
RPOST nOP_OUT nVC
6 7
nOP_IN
VC
Figure 4: External Loop Filter
See Example External Loop Filter Component Values table.
PLL bandwidth is affected by loop filter component values, "Mfec" and "Mfin" values, and the "PLL Loop Constants" listed in AC Characteristics on pg. 8. The various "Non-FEC ratio" settings can be used to actively change PLL loop bandwidth in a given application. See "FEC PLL Ratio Dividers Look-up Table (LUT)" on pg. 3. PLL Simulator Tool Available A free PC software utility is available on the ICS website (www.icst.com). The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application.
Go to the SAW PLL Simulator Software web page at www.icst.com/products/calculators/m2000filterSWdesc.htm
Example External Loop Filter Component Values1
VCSO Parameters: KVCO = 800kHz/V, RIN = 50k, VCSO Bandwidth = 700kHz. Device Configuration (MHz) Example External Loop Filter Component Values pins Nominal Performance Using These Values
FRef
FVCSO (MHz) FIN_SEL1:0 FEC_ SEL3:0
pins
R loop 11.5k
C loop 2.2F
R post 34k
C post 470pF
PLL Loop Bandwidth 1kHz
Damping Passband Factor Peaking (dB) 6.0 0.05
19.44 77.76 155.52 622.08 167.3317 669.3266 155.52 622.08
622.08
00 01 10 11 10 11
1100 1110 1111 0110 0001 1001
5.11k 113.0k 28.0k 121.0k 30.1k
4.7F 0.22F 1.0F 0.22F 1.0F
6.0 6.0 6.3 6.0 6.5
0.06 0.06 0.05 0.05 0.05
669.3266
10 11
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Table 8: Example External Loop Filter Component Values
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M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter Rating Unit
VI VO VCC TS
Inputs Outputs Power Supply Voltage Storage Temperature
-0.5 to VCC +0.5 -0.5 to VCC +0.5
4.6
V V V
o
-45 to +100
C
Table 9: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter Min 3.135 Typ 3.3 Max 3.465 Unit
VCC TA
Positive Supply Voltage Ambient Operating Temperature Commercial Industrial
V
oC oC
0 -40
+70 +85
Table 10: Recommended Conditions of Operation
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M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz, LVPECL outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min 3.135
Typ 3.3 175
Max 3.465 225
Unit Conditions
Power Supply VCC ICC All Differential Inputs Differential Inputs with Pull-down Differential Inputs with Pull-up All LVCMOS / LVTTL Inputs LVCMOS / LVTTL Inputs with Pull-down LVCMOS / LVTTL Inputs with Pull-up Differential Outputs VP-P VCMR CIN IIH IIL IIH IIL Rpullup VIH VIL CIN IIH IIL IIH IIL Rpullup VOH VOL VP-P
Positive Supply Voltage Power Supply Current Peak to Peak Input Voltage Common Mode Input Input Capacitance Input High Current (Pull-down) Input Low Current (Pull-down) Input High Current (Pull-up) Input Low Current (Pull-up) Internal Pull-up Resistance Input High Voltage Input Low Voltage Input Capacitance Input High Current (Pull-down) Input Low Current (Pull-down) Input High Current (Pull-up) Input Low Current (Pull-up) Internal Pull-up Resistance Output High Voltage Output Low Voltage Peak to Peak Output Voltage 1
FOUT0, nFOUT0, FOUT1, nFOUT1 FEC_SEL3, FEC_SEL2, FEC_SEL1, FEC_SEL0 REF_SEL, FIN_SEL1, FIN_SEL0, P1_SEL, P0_SEL APC, REF_SEL, FIN_SEL1, FIN_SEL0, FEC_SEL3, FEC_SEL2, FEC_SEL1, FEC_SEL0, P1_SEL, P0_SEL nDIF_REF0, nDIF_REF1 DIF_REF0, DIF_REF1 DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1
V mA V
0.15 0.5
Vcc - .85 V 4 150
pF A A k
VCC = VIN = 3.456V
-5
50 5
Rpulldown Internal Pull-down Resistance -150
A A k
VIN = 0 to 3.456V
50 2
Vcc + 0.3 V 0.8 4 150
-0.3
V pF A A k
VCC = VIN = 3.456V
-5
50
Rpulldown Internal Pull-down Resistance -150
5
50 Vcc - 1.4 Vcc - 2.0 0.4
A A k
VCC = 3.456V VIN = 0 V
Vcc - 1.0 V Vcc - 1.7 V 0.85
V
Note 1: Single-ended measurement. See Figure 5, Output Rise and Fall Time, on pg. 8.
Table 11: DC Characteristics
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M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz, LVPECL outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 FOUT0, nFOUT0, FOUT1, nFOUT1 Commercial Industrial 10
Typ
Max 700
Unit Test Conditions
Input Frequency Range Output Frequency
FIN
Input Frequency
MHz
FFOUT APR
Output Frequency Range VCSO Pull-Range VCO Gain Internal Loop Resistor Single Side Band Phase Noise @622.08MHz Jitter (rms) @622.08MHz Output Duty Cycle
FOUT0, nFOUT0, FOUT1, nFOUT1
2
100
700
MHz ppm ppm kHz/V k kHz dBc/Hz Fin=19.44 MHz dBc/Hz Mfin=32, Mfec=1, Rfec=1 dBc/Hz ps rms ps rms % % ps ps
20% to 80% 20% to 80%
120 50
200 150
800 50 700
PLL Loop Constants 1
KVCO RIN n
BWVCSO VCSO Bandwidth
1kHz Offset 10kHz Offset 100kHz Offset 12kHz to 20MHz 50kHz to 80MHz
P0, P1 = 1 P0, P1 = 4
Phase Noise and Jitter J(t) tPW tR tF
-72 -94 -123
0.25 0.25 40 45 200 200 50 50 450 450 0.5 0.5 60 55 500 500
Output Rise Time 2 Output Fall Time 2
FOUT0, nFOUT0, FOUT1, nFOUT1
Table 12: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see PLL Simulator Tool Available on pg. 5. Note 2: See Parameter Measurement Information on pg. 8.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time Output Duty Cycle
nFOUT FOUT VP-P Clock Output 20% tR 20% tF odc = tPW tPERIOD tPW (Output Pulse Width) tPERIOD
80%
80%
Figure 5: Output Rise and Fall Time
Figure 6: Output Duty Cycle
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M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Refer to the SAW PLL application notes web page at www.icst.com/products/appnotes/SawPllAppNotes.htm for application notes, including recommended PCB footprint, solder mask, and furnace profile.
Figure 7: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
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M2006-12A
VCSO BASED FEC CLOCK PLL WITH HITLESS
Standard VCSO Output Frequencies (MHz)*
Consult ICS for the availablity of other VCSO frequencies
ORDERING INFORMATION
Part Numbering Scheme Part Number:
Device Number Temperature " - " = 0 to +70 oC (commercial) I = - 40 to +85 oC (industrial) VCSO Frequency (MHz) See Table 13, right. Consult ICS for other frequencies.
622.0800
669.3120 669.3266 669.6429 670.8386 672.1600 690.5692
M2006- 12A - xxx.xxxx
625.0000 627.3296 644.5313 666.5143 669.1281
Table 13: Standard VCSO Output Frequencies (MHz)
Figure 8: Part Numbering Scheme
Note *: Fout can equal Fvcso divided by: 1 or 4
Consult ICS for the availability of other PLL frequencies.
Example Part Numbers
PLL Frequency (MHz) 622.08 625.00 669.3266 669.6429
Temperature
commercial industrial commercial industrial commercial industrial commercial industrial
Order Part Number M2006-12A - 622.0800 M2006-12AI622.0800 M2006-12A - 625.0000 M2006-12AI625.0000 M2006-12A - 669.3266 M2006-12AI669.3266 M2006-12A - 669.6429 M2006-12AI669.6429
Table 14: Example Part Numbers
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Price & Availability of M2006-12A-6220800

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